1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device that is formed by a layout design using a standard cell system.
2. Description of the Related Art
In a layout design of a semiconductor integrated circuit device using a standard cell system, a layout generation tool called a place and route tool (P and R tool) is used. The automatic layout wiring tool is for obtaining a desired semiconductor integrated circuit device, by registering in advance standard cells into a standard cell library as a database, reading data of the standard cells of a desired basic circuit from the database, and arraying and wiring the data in a predetermined region. In the standard cells, there are cells such as an inverter, a NAND, and an NOR that achieve mutually different logics and functions. For a majority of the standard cells that are included in the standard cell library, layout of the standard cells is generated, by prioritizing a minimum rule that is prescribed by a design rule.
In recent years, miniaturization of a manufacturing process in a semiconductor integrated circuit device is progressed, and a gate length of a gate tends to become increasingly shorter. The gate length is a distance between a drain and a source of a MOS transistor. In the semiconductor integrated circuit device that uses the standard cell system, it is becoming difficult to simultaneously achieve both suppression of leak current of a device and increase of on-current, due to development of the miniaturization process. That is, although on-current can be increased by shortening a gate length, leak current also increases. Therefore, in a high-performance chip of large on-current, leak current increases, and this becomes a cause of an increase in power consumption.
To suppress leak current, there is a method of forming a semiconductor integrated circuit device corresponding to performance, by preparing a standard cell that uses a device of high performance and much leak current, and a standard cell that uses a device of low performance and little leak current, and by selectively combining these standard cells in processes of synthesis and P and R tool.
As a method of separately manufacturing a device of high performance and much leak current and a device of little leak current, there is a method of separately manufacturing devices of plural threshold voltages Vt, by including plural sets of injection masks, and by controlling the threshold voltage Vt of the devices, and a method of separately manufacturing devices of plural gate lengths by adjusting layout of a gate length. The method of controlling a gate length is advantageous in cost and a cycle time as compared with the method of controlling the threshold voltage Vt, because there is no increase in injection masks and injection processes.
Patent Document 1 discloses a layout configuration of standard cells that makes it possible to control a gate length to suppress leak current. The standard cells include gates of MOS transistors, and regions for extending a gate length between adjacent contacts. Layout is improved to be able to suppress leak current without changing existing processes.
FIGS. 15A and 15B show examples of layout of standard cells disclosed in Patent Document 1. The layout of standard cells shown in FIG. 15A includes a region for arraying an extension poly between gate poly 101 and adjacent contacts 102. That is, a distance Space-2 between gate poly 101 and contacts 102 is set greater than a minimum distance that is prescribed by the design rule. With this arrangement, the extension poly can be arrayed without changing layout other than that of gate poly 101. A gate length can be extended by only revising a gate poly, and a short-channel effect can be suppressed. FIG. 15B shows a layout example in which extension poly 103 is arrayed (see FIG. 2 in Patent Document 1: Unexamined Japanese Patent Publication No. 2005-236210).